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SCAN182374A D-Type Flip-Flop with 25 Series Resistor Outputs
January 1993 Revised August 2000
SCAN182374A D-Type Flip-Flop with 25 Series Resistor Outputs
General Description
The SCAN182374A is a high performance BiCMOS D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK).
Features
s IEEE 1149.1 (JTAG) Compliant s High performance BiCMOS technology s 25 series resistor outputs eliminate need for external terminating resistors s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s 25 mil pitch SSOP (Shrink Small Outline Package) s Includes CLAMP, IDCODE and HIGHZ instructions s Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT s Power up 3-STATE for hot insert s Member of Fairchild's SCAN Products
Ordering Code:
Order Number SCAN182374ASSC Package Number MS56A Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Device also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names AI(0-8), BI(0-8) ACP, BCP AOE1, BOE1 AO(0-8), BO(0-8) Description Data Inputs Clock Pulse Inputs 3-STATE Output Enable Inputs 3-STATE Outputs
Truth Tables
Inputs ACP AOE1 (Note 1) H L L Inputs BCP BOE1 (Note 1) H L L BI(0-8) X L H BO(0-8) Z L H AI(0-8) X L H AO(0-8) Z L H

X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

X
Z = High Impedance = L-to-H Transition
Note 1: Inactive-to-active transition must occur to enable outputs upon power-up.
(c) 2000 Fairchild Semiconductor Corporation
DS011545
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SCAN182374A
Functional Description
The SCAN182374A consists of two sets of nine edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable pins are common to all flip-flops. Each set of the nine flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (ACP or BCP) transition. With the Output Enable (AOE1 or BOE1) LOW, the contents of the nine flip-flops are available at the outputs. When the Output Enable is HIGH, the outputs go to the high impedance state. Operation of the Output Enable input does not affect the state of the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
Byte-A
Note: BSR stands for Boundary Scan Register
Tap Controller
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Block Diagrams
(Continued) Byte-B
Note: BSR stands for BOUNDARY-SCAN Register
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 MSB LSB Instruction Code 00000000 SCAN182374A Product IDCODE (32-Bit Code per IEEE 1149.1) Version Entity 0000 MSB Per Number Manufacturer Required ID by 1149.1 1 LSB 10000001 10000010 00000011 01000001 01000010 00100010 10101010 11111111 All Other Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGH-Z SAMPLE-IN SAMPLE-OUT EXTEST-OUT IDCODE BYPASS BYPASS The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR EXIT1-IR UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. Instruction Register Scan Chain Definition
111111 0000000111 00000001111
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SCAN182374A
Description of BOUNDARY-SCAN Circuitry
Scan Cell TYPE1
(Continued)
Scan Cell TYPE2
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Description of BOUNDARY-SCAN Circuitry
(Continued) BOUNDARY-SCAN Register SCAN182374A Scan Chain Definition (42 Bits in Length)
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Description of BOUNDARY-SCAN Circuitry
(Continued) Input BOUNDARY-SCAN Register Scan Chain Definition (22 Bits in Length) When Sample In is Active
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Description of BOUNDARY-SCAN Circuitry
(Continued) Output BOUNDARY-SCAN Register Scan Chain Definition (20 Bits in Length) When Sample Out and EXTEST Out are Active
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Description of BOUNDARY-SCAN Circuitry
Bit No. 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pin Name AOE1 ACP AOE BOE1 BCP BOE AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 AI8 BI0 BI1 BI2 BI3 BI4 BI5 BI6 BI7 BI8 AO0 AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 BO0 BO1 BO2 BO3 BO4 BO5 BO6 BO7 BO8 55 53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32 30 2 4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25 27 26 31 Pin No. 3 54
(Continued) BOUNDARY-SCAN Register Definition Index Pin Type Input Input Internal Input Input Internal Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Scan Cell Type TYPE1 TYPE1 TYPE2 TYPE1 TYPE1 TYPE2 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 B-out A-out B-in A-in Control Signals
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SCAN182374A
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) ESD (HBM) Min. Twice the Rated IOL (mA)
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate Data Input Enable Input
-40C to +85C +4.5V to +5.5V
(V/t) 50 mV/ns 20 mV/ns
-0.5V to +5.5V -0.5V to VCC
-500 mA
10V 2000V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current All Others TMS, TDI Inputs IBVI IBVIT IIL Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current All Others TMS, TDI VID IIH + IOZH IIL + IOZL IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Input Leakage Test Output Leakage Current Output Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC All Other Inputs TDI, TMS Inputs No Load Min Min Min Min Max Max Max Max Max Max Max Max 0.0 Max Max Max Max Max Max 0.0 Max Max Max Max Max Max Max Max Max -100 4.75 50 -50 50 -50 -275 50 100 250 1.0 65 65.8 250 1.0 2.9 3 0.2 2.5 2.0 0.8 5 5 5 7 100 -5 -5 -385 VCC Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A A A A A A V A A A A mA A A A mA mA mA A mA mA mA mA/ MHz
Note 4: Guaranteed not tested.
Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 15 mA VIN = 2.7V (Note 4) VIN = VCC VIN = VCC VIN = 7.0V VIN = 5.5V VIN = 0.5V (Note 4) VIN = 0.0V VIN = 0.0V IID = 1.9 A All Other Pins Grounded VOUT = 2.7V VOUT = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0.0V VOUT = VCC VOUT = 5.5V All Others Grounded VOUT = VCC; TDI, TMS = VCC VOUT = VCC; TDI, TMS = GND VOUT = LOW; TDI, TMS = VCC VOUT = LOW; TDI, TMS = GND TDI, TMS = VCC TDI, TMS = GND VIN = VCC - 2.1V VIN = VCC - 2.1V Outputs Open One Bit Toggling, 50% Duty Cycle
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SCAN182374A
AC Electrical Characteristics
Normal Operation VCC Symbol Parameter (V) (Note 5) tPLH tPHL tPLZ tPHZ tPZL tPZH
Note 5: Voltage Range 5.0V 0.5V
TA = -40C to +85C CL = 50 pF Min 1.4 2.1 1.9 1.8 2.0 1.4 Typ 4.6 4.9 4.6 4.8 6.7 6.0 Max 6.1 6.8 8.0 8.7 9.4 8.2 ns ns ns Units
Propagation Delay CP to Q Disable Time Enable Time
5.0 5.0 5.0
AC Operating Requirements
Normal Operation VCC Symbol Parameter (V) (Note 6) tS tH tW fMAX Setup Time, H or L Data to CP Hold Time, H or L CP to Data CP Pulse Width Maximum ACP/BCP Clock Frequency
Note 6: Voltage Range is 5.0V 0.5V.
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 2.8 2.4 0.0 50 ns ns ns MHz Units
5.0 5.0 5.0 5.0
AC Electrical Characteristics
Scan Test Operation VCC Symbol Parameter (V) (Note 7) tPLH tPHL tPLZ tPHZ tPZL tPZH tPLH tPHL tPLH tPHL tPLH tPHL tPLZ tPHZ tPLZ tPHZ tPLZ tPHZ tPZL tPZH tPZL tPZH tPZL tPZH Propagation Delay TCK to TDO Disable Time TCK to TDO Enable Time TCK to TDO Propagation Delay TCK to Data Out during Update-DR State Propagation Delay TCK to Data Out during Update-IR State Propagation Delay TCK to Data Out during Test Logic Reset State Disable Time TCK to Data Out during Update-DR State Disable Time TCK to Data Out during Update-IR State Disable Time TCK to Data Out during Test Logic Reset State Enable Time TCK to Data Out during Update-DR State Enable Time TCK to Data Out during Update-IR State Enable Time TCK to Data Out during Test Logic Reset State 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Min 2.9 4.0 1.9 3.0 4.4 2.7 3.4 4.3 3.9 4.7 4.7 5.6 3.2 3.9 3.2 3.8 4.2 5.0 5.0 3.7 5.3 4.0 6.2 4.7 TA = -40C to +85C CL = 50 pF Typ 5.8 7.3 5.6 7.1 8.4 6.4 6.5 8.1 7.8 9.1 9.5 10.9 7.8 8.5 8.6 9.3 10.2 11.0 9.6 7.7 10.8 9.0 12.6 10.7 Max 9.5 11.5 10.0 12.1 13.2 10.9 10.5 12.7 12.8 14.5 15.6 17.4 13.6 14.2 15.0 15.6 18.0 18.5 15.3 13.0 17.4 15.1 20.4 18.1 ns ns ns ns ns ns ns ns ns ns ns ns Units
Note 7: Voltage Range 5.0V 0.5V
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AC Operating Requirements
Scan Test Operation VCC Symbol Parameter (V) (Note 8) tS tH tS tH tS tH tS tH tS tH tS tH tW fMAX tPU tDN Setup Time Data to TCK (Note 9) Hold Time Data to TCK (Note 9) Setup Time, H or L AOE1, BOE1 to TCK (Note 10) Hold Time, H or L TCK to AOE1, BOE1 (Note 10) Setup Time, H or L Internal AOE, BOE to TCK (Note 11) Hold Time, H or L TCK to Internal AOE, BOE (Note 11) Setup Time ACP, BCP (Note 12) to TCK Hold Time TCK to ACP, BCP (Note 12) Setup Time, H or L TMS to TCK Hold Time, H or L TCK to TMS Setup Time, H or L TDI to TCK Hold Time, H or L TCK to TDI Pulse Width TCK Maximum TCK Clock Frequency Wait Time, Power Up to TCK Power Down Delay H L 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0.0 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 2.7 3.1 5.0 1.8 3.6 2.1 3.4 1.8 8.7 1.8 6.4 3.2 8.2 11.2 50 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ms Units
Note 8: Voltage Range 5.0V 0.5V Note 9: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35. Note 10: Timing pertains to BSR 38 and 41 only. Note 11: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. Note 12: Timing pertains to BSR 37 and 40 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Capacitance
TA = 25C Symbol CIN Input Capacitance Parameter Typ 5.8 13.8 Units pF pF VCC = 0.0V VCC = 5.0V Conditions
COUT (Note 13) Output Capacitance
Note 13: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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SCAN182374A D-Type Flip-Flop with 25 Series Resistor Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 12 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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